I am a fourth year Computer Engineering PhD candidate at SCALE lab at Brown University, advised by Professor Sherief Reda and Professor Jacob Rosenstein. I am interested in leveraging AI for accelerating hardware design workflows. My research focuses on integrating AI across the entire lifecycle of microelectroninc systems from intial design conceptuatialization to applications, with the aim of driving a faster and an insightful hardware design process.

Before joining Brown, I worked as an EDA engineer at efabless, where I worked on developing open-source ASIC and contributed to the OpenLane, and Caravel projects.

I earned my bachelors in Computer Engineering from the American University in Cairo, where I was involved with research activities at the AUCOHL lab, advised by Professor Mohamed Shalan. I worked on developing an open-source DFT toolchain (Fault)

Research

My research focuses on leveraging AI for accelerating and driving insights in hardware design workflows:

1. LLM-Powered Framework for PDK and Hardware Design Queries
   

   In this project, I am building ChipXplore, a framework powered by large language models (LLMs) to query Process Design Kits (PDKs) and hardware designs. The aim is to enable streamlined, natural language-based interactions with PDKs and hardware designs, automating data retrieval and analysis to enhance accessibility and overall design efficiency.

2. LLMs for Verilog Code Metric Reasoning
   

   In MetRex (ASP-DAC'25), we investigate the use of large language models to reason about Verilog code metrics to provide insights into the quality, efficiency, and performance of hardware designs.

3. AI for Post-Silicon Data Analysis in Biosensors
   

   In collaboration with interdesipllinary teams, this project focuses on using AI to analyze data from CMOS biosensors BioCAS'23, TBioCAS'24. The objective is to develop AI-driven insights to better understand sensor operation with biological interfaces, particularly regarding measurement depth and which measurements have high fidelty. Using these insights, the project aims to provide feedback that guides improvements in the next generation of the sensor.

Publications

Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code
M. Abdelatty*, M. Nouh*, J. Rosenstein, S. Reda
Preprint | Paper

ChipXplore: Natural Language Exploration of Hardware Designs and Libraries
(🏆 Best Paper Award)
M. Abdelatty, J. Rosenstein, S. Reda
IEEE International Conference on LLM-Aided Design (LAD) | GitHub | Slides | Paper

MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
M. Abdelatty,J. Ma, S. Reda
IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) 2025 | GitHub | Slides | Paper

Electrical Capacitance Tomography of Cell Cultures on a CMOS Microelectrode Array
M. Abdelatty, J. T. Incandela, K. Hu, P. Joshi, J. W. Larkin, S. Reda, and J. K. Rosenstein
IEEE Transactions on Biomedical Circuits and Systems. (TBioCAS),2024 | Paper

Microscale 3-D Capacitance Tomography with a CMOS Sensor Array
M. Abdelatty, J. T. Incandela, K. Hu, J. W. Larkin, S. Reda, and J. K. Rosenstein
IEEE Biomedical Circuits and Systems (BioCAS), 2023. | Slides | Paper

Fault: Open Source EDA's Missing DFT Toolchain
M. Abdelatty, M. Gaber, and M. Shalan
IEEE Design & Test | Github | Slides | Paper

Fault, an Open Source DFT Toolchain
M. Gaber, M. Abdelatty and M. Shalan
Workshop on Open-Source EDA Technology (WOSET), 2019 | Github | Slides | Paper

Work Experience

Teaching Experience